The trench isolation structure and process is important for the manufacture of a semiconductor device to isolate microelectronic devices in the semiconductor device. For the microelectronic devices to be placed increasing closer to each other without causing detrimental electronic interaction such as unwanted capacitance build-up and current leakage, advanced trench isolation structure and process is desired.
In a conventional trench isolation, an isolation trench is formed in a semiconductor substrate and then filled up with an isolation material, and the active area of the semiconductor substrate is covered with a pad oxide thereon. However, the isolation material in the isolation trench exhibits a non-planarity at the top surface thereof between corners due to dissimilarity of etch rates between the isolation material and pad oxide. A problem that is inherent in such non-planarity of fill material within an isolation trench is that the corners may leave the active area of the semiconductor substrate exposed. As a result, the isolation material will not prevent layers formed thereon contacting the active area of the semiconductor substrate at the corners, which is detrimental in that it causes charge and current leakage. The isolation material is also unable to prevent unwanted thermal oxide encroachment through the corners into the active area of the semiconductor substrate.
Gonzalez et al. disclose a self-aligned isolation trench and a method of forming such an isolation trench structure without causing deleterious topographical depressions in upper surface thereof which cause current and charge leakage to an adjacent active area, respectively in U.S. Pat. Nos. 6,097,076 and 5,953,621. These prior arts form a nitride layer on the pad oxide which is grown upon a semiconductor substrate. After patterning the nitride layer to expose a portion of the pad oxide layer, a second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of a first dielectric layers. A spacer is formed from the second dielectric layer, and then an isolation trench is etched into the semiconductor substrate. A conformal layer is formed substantially conformably over the spacer and the remaining portions of the first dielectric layer, and substantially filling in the isolation trench. After planarization of the conformal layer, the resulting structure has a flange and shaft, the cross section of which has a nail shape in its cross section.
However, even though Gonzalez et al. improve the trench isolation by the above-described arts, the method of forming the isolation trench is still complicated. It is therefore desired a further improvement for the trench isolation process over the method provided by Gonzalez et al.